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| 19-2086; Rev 1; 12/02 +3.3V, 10.3Gbps Limiting Amplifier General Description The MAX3971 is a compact, low-power, 10.3Gbps limiting amplifier. It accepts signals over a wide range of input voltage levels and provides constant-level output voltages with controlled edge speeds. It functions as a data quantizer. The output of the amplifier is a 250mVP-P differential CML signal with a 100 differential termination. The MAX3971 is designed to work with the MAX3970, a 10.3Gbps transimpedance amplifier (TIA). The limiting amplifier operates on a single +3.3V supply and consumes only 155mW. The part functions over the 0C to +85C temperature range. It also has a disable function that allows the outputs to be squelched if required by the application. The MAX3971 is offered in die form and in a compact 4mm x 4mm, 20-pin QFN plastic package. ____________________________Features o Single +3.3V Power Supply o 155mW Power Consumption o 9.5mVP-P Input Sensitivity o 800mVP-P Input Overload o 3.4psP-P Deterministic Jitter o Dice and 4mm x 4mm QFN Packages o Output Disable Feature MAX3971 Applications 10-Gigabit Ethernet Optical Receivers VSR OC-192 Receivers 10-Gigabit Fibre Channel Receivers PART MAX3971UGP MAX3971U/D Ordering Information TEMP. RANGE 0C to +85C 0C to +85C PIN-PACKAGE 20 QFN* Dice** *Exposed pad **Dice are designed to operate over a 0C to +110C junction temperature (TJ) range, but are tested and guaranteed at TA = +25C. Pin Configuration appears at end of data sheet. Typical Application Circuit +3.3V 0.1F +3.3V CZGNDIN+ 0.1F IN+ 100 INGNDINOUTOUT+ 0.1F CZ+ SUPPLY FILTER VCC1 VCC2 VCC3 TIA 0.1F 0.1F 100 MAX3970 MAX3971 DISABLE ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. +3.3V, 10.3Gbps Limiting Amplifier MAX3971 ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC1, VCC2, VCC3 .......................-0.5V to +0.5V Voltage at IN+, IN-, DISABLE, CZ+, CZ-, OUT+, OUT-........................+0.5V to (VCC + 0.5V) Differential Voltage Between CZ+ and CZ- ...........................1V Differential Voltage Between IN+ and IN-...........................2.5V Continuous Power Dissipation (TA = +85C) 20-Lead QFN (derate 20mW/C above +85C) ..............1.3W Operating Ambient Temperature Range .............-40C to +85C Storage Temperature Range .............................-55C to +150C Die Attach Temperature...................................................+400C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at VCC = +3.3V, output load = 50 to VCC, TA = +25C, unless otherwise noted. Data mark density is 50%.) PARAMETER Supply Current Small-Signal Bandwidth Low-Frequency Cutoff Data Rate 10mVP-P input, K28.5 pattern at 10.3Gbps (Note 1) Deterministic Jitter 20mVP-P input, K28.5 pattern at 10.3Gbps (Note 1) 800mVP-P input, K28.5 pattern at 10.3Gbps (Note 1) Random Jitter Transition Time, Output Input Sensitivity Input Overload Data Input Resistance Differential Data Output-Voltage Swing Data Output Common-Mode Voltage Output Resistance Data Output Offset when DISABLE is High DISABLE Input Current DISABLE Input High Voltage DISABLE Input Low Voltage High = VCC, low = GND 2.8 1.4 tr, tf VIN-min VIN-max RIN VOD1 VOD2 VCM ROUT Single-ended 42 Single-ended DISABLE high DISABLE low 190 20mVP-P to 800mVP-P (Note 2) 20% to 80%, OUT+, OUTBER = 1E-12, 223 - 1PRBS, 10.3Gbps 800 42 52 1 250 VCC 0.75 52 75 0.05 1 58 58 50 400 SYMBOL ICC BW CZ = 0.1F CONDITIONS MIN TYP 47 10 40 10 8 4.7 3.4 0.7 20 14 7 1.0 30 9.5 psRMS ps mVP-P mVP-P mVP-P V mVP-P mA V V psP-P 160 MAX 85 UNITS mA GHz kHz Gbps Note 1: Note 2: Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). It is the peak-to-peak deviation from the ideal time crossings, measured at the zero-level crossings of the differential output. Random jitter is measured with the minimum input signal applied. To achieve a bit error rate of 10-12, the peak-to-peak random jitter is 14.1 times the RMS random jitter. 2 _______________________________________________________________________________________ +3.3V, 10.3Gbps Limiting Amplifier Typical Operating Characteristics (VCC = +3.3V, output load = 50 to VCC, TA = +25C, unless otherwise noted.) OUTPUT EYE DIAGRAM (INPUT SIGNAL = 800mVP-P AT 10.3Gbps) MAX3971 toc02 MAX3971 SUPPLY CURRENT vs. TEMPERATURE MAX3971 toc01 OUTPUT EYE DIAGRAM (INPUT SIGNAL = 9mVP-P AT 10.3Gbps) MAX3971 toc03 70 65 SUPPLY CURRENT (mA) 60 55 50 45 40 0 10 20 30 40 50 60 70 80 50mV/div 50mV/div 90 20ps/div 20ps/div TEMPERATURE (C) TRANSITION TIME vs. TEMPERATURE (20% to 80%) MAX3971 toc04 DETERMINISTIC JITTER vs. TEMPERATURE (800mVP-P INPUT K28.5 PATTERN AT 10.3Gbps) 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 0 MAX3971 toc05 DETERMINISTIC JITTER vs. TEMPERATURE (10mVP-P INPUT K28.5 PATTERN AT 10.3Gbps) 8.0 7.8 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 5.8 5.6 5.4 5.2 5.0 0 (1) VCC = +3.0V (2) VCC = +3.6V MAX3971 toc06 22 (1) VCC = +3.0V, INPUT = 800mVP-P (2) VCC = +3.6V, INPUT = 800mVP-P (1) VCC = +3.0V (2) VCC = +3.6V JITTER (psP-P) (1) (2) 20 (2) JITTER (psP-P) 21 TIME (ps) (1) (1) (2) 19 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) 10 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) TEMPERATURE (C) INPUT SENSITIVITY vs. TEMPERATURE (FOR BIT-ERROR RATIO OF 1E-12) MAX3971 toc07 INPUT RETURN (S11) INPUT SIGNAL = -20dBm MAX3971 toc08 OUTPUT RETURN (S22) INPUT SIGNAL = -20dBm MAX3971 toc09 11 10 0 -10 10 0 -10 GAIN (dB) -20 -30 -40 -50 SIGNAL INPUT LEVEL (mVP-P) 10 GAIN (dB) 10 20 30 40 50 60 70 80 90 9 -20 -30 8 -40 7 TEMPERATURE (C) -50 100 2100 4100 6100 FREQUENCY (MHz) 8100 10,100 100 2100 4100 6100 FREQUENCY (MHz) 8100 10,100 _______________________________________________________________________________________ 3 +3.3V, 10.3Gbps Limiting Amplifier MAX3971 Typical Operating Characteristics (continued) (VCC = +3.3V, output load = 50 to VCC, TA = +25C, unless otherwise noted.) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY MAX3971 toc10 COMMON-MODE REJECTION RATIO vs. FREQUENCY MAX3971 toc11 60 50 40 PSRR (dB) 30 20 10 0 1 10 100 60 50 40 CMMR (dB) 30 20 10 0 1000 1 10 100 FREQUENCY (MHz) 1000 10,000 FREQUENCY (MHz) Pin Description PIN 1 2 3 4 5, 7, 9, 10 6, 8, 11 12, 15 13 14 16 17 18 19 20 EP NAME GNDIN+ IN+ INGNDINN.C. GND VCC3 OUTOUT+ DISABLE VCC2 CZ+ CZVCC1 Exposed Pad FUNCTION Input Ground for Shielding Input Signal IN+. Not connected internally. Noninverting Input Signal Inverting Input Signal Input Ground for Shielding Input Signal IN-. Not connected internally. No Connection. Leave unconnected. Ground Output Circuitry Power Supply Inverting Output of Amplifier Noninverting Output of Amplifier When High, the Outputs are Disabled Power Supply to Circuitry Other than Input and Output Circuits Filter Capacitor for Offset Correction. Attach other side of a capacitor to pin 19. See the Detailed Description. See pin 18. Input Circuitry Power Supply Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation. 4 _______________________________________________________________________________________ +3.3V, 10.3Gbps Limiting Amplifier Detailed Description and Applications Information Figure 1 is a functional diagram of the MAX3971 limiting amplifier.The signal path consists of an input buffer followed by a gain stage and output amplifier. A feedback loop provides offset correction by driving the average value of the differential output to zero. product of an equivalent 20k on-chip resistor and the value of the off-chip capacitor, CZ. For stable operation, the minimum value of CZ is 0.01F. To minimize pattern-dependent jitter, CZ should be as large as possible. For 10-Gigabit Ethernet applications, the typical value of CZ is 0.1F. Keep CZ as close to the package as possible. MAX3971 CML Input Circuit The input buffer is designed to accept CML input signals such as the output from the MAX3970 transimpedance amplifier. An equivalent circuit for the input is shown in Figure 2. DC-coupling the inputs is not recommended because doing so prevents the part's offset correction circuitry from working properly. Thus, ACcoupling capacitors are required on the input. Gain Stage and Offset Correction The limiting amplifier provides approximately 50dB gain. This large gain makes the amplifier susceptible to small DC offsets, which cause deterministic jitter. A low-frequency loop is integrated into the limiting amplifier to reduce output offset, typically to less than 2mV. The external capacitor CZ is required to set the low-frequency cutoff for the offset correction loop and for stability. The time constant of the loop is set by the CZ CML Output Circuit An equivalent circuit for the output network is shown in Figure 3. It consists of two 50 resistors connected to VCC driven by the collectors of an output differential transistor pair (Q1 and Q2). The differential output signals are clamped by transistors Q3 and Q4 when the DISABLE input is high. CZ- CZ+ DISABLE MAX3971 GNDIN+ IN+ INPUT AMPLIFIER IN- OFFSET CORRECTION AMP LOWPASS FILTER Disable Function A logic signal can be applied to the DISABLE pin to squelch the output signal. When the output is disabled, an offset is added to the output, preventing the following stage from oscillating (if DC-coupled). OUT+ GAIN 50dB OUTPUT AMPLIFIER OUT- GNDIN- Figure 1. Functional Diagram VCC1 VCC3 GNDIN+ 50 50 50 50 OUT+ OUT- IN+ DISABLE Q3 Q4 Q1 Q2 INGNDINDATA ESD STRUCTURES ESD STRUCTURES Figure 2. CML Input Equivalent Circuit Figure 3. CML Input Equivalent Circuit Showing Clamping Circuit for Squelching the Output Signal 5 _______________________________________________________________________________________ +3.3V, 10.3Gbps Limiting Amplifier MAX3971 Layout Considerations Circuit board layout and design can significantly affect the MAX3971's performance. Use good high-frequency techniques, including fixed-impedance transmission lines for the high-frequency data signal. Use a multilayer board with solid ground plane. Minimize the inductance between MAX3971 and the ground plane. The MAX3971 uses three power supply pins (VCC1, VCC2, VCC3). The input circuitry of the MAX3971 is supplied by VCC1. The output drivers have a separate supply (VCC3), which usually has large pulsing currents. All other circuitry is powered by VCC2. It is possible to simply connect the three pins together. However, better isolation of the input circuitry is ensured by using a supply filter. For optimal isolation, Figure 4 shows a possible supply filtering circuit. Element L, a ferrite bead, provides isolation between a noisy VCC3 and sensitive VCC1. +3.3V L SUPPLY FILTER C = 0.001F C = 0.001F C = 0.001F VCC1 VCC2 VCC3 MAX3971 Figure 4. Power-Supply Filter Pin Configuration DISABLE VCC1 VCC2 CZ+ CZ- Chip Information TRANSISTOR COUNT: 1803 PROCCESS: SiGe Bipolar SUBSTRATE: Electrically Isolated 20 1 2 3 4 5 19 18 17 16 15 VCC3 14 OUT+ GNDIN+ IN+ INGNDINN.C. MAX3971 13 OUT12 VCC3 11 GND 6 GND 7 N.C. 8 GND 9 N.C. 10 N.C. 20 QFN 6 _______________________________________________________________________________________ +3.3V, 10.3Gbps Limiting Amplifier Chip Topography VCC1 CZCZ+ VCC2 DISABLE MAX3971 GNDIN+ VCC3 IN+ OUT+ IN- OUT0.045" (1.15mm) GNDIN- VCC3 N.C. GND GND N.C. GND 0.049" (1.25mm) N.C. N.C. _______________________________________________________________________________________ 7 +3.3V, 10.3Gbps Limiting Amplifier MAX3971 Chip Topography (continued) MAX3971 PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 X DIMENSION (MICRONS) 0 0 0 0 0 163.8 289.8 415.8 541.8 667.8 884.8 884.8 884.8 884.8 884.8 667.8 541.8 415.8 289.8 163.8 Y DIMENSION (MICRONS) 672 546 420 294 168 0 0 0 0 0 168 294 420 546 672 772.8 772.8 772.8 772.8 772.8 (0,0) 6 7 2 3 1 Y 14 13 20 19 18 17 16 * * All dimensions are in microns. Pad dimensions: PASSIVATION OPENING: 94.4 microns x 94.4 microns METAL: 102.4 microns x 102.4 microns * All measurements specify the lower left corner of the pad 15 MAX3971 4 5 X 8 9 10 12 11 8 _______________________________________________________________________________________ +3.3V, 10.3Gbps Limiting Amplifier Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX3971 _______________________________________________________________________________________ 12,16,20, 24L QFN.EPS 9 +3.3V, 10.3Gbps Limiting Amplifier MAX3971 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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